1. Field of the Invention
The present invention is related to integrated circuits incorporating resonant clocking schemes, and more specifically to techniques for controlling pulse widths of resonant clocking drive circuits during operation.
2. Description of Related Art
Resonant clocking of digital integrated circuits provides low energy consumption and well-controlled clock characteristics, including reduction of jitter and predictable point-to-point delay. In some implementations, a reduced pulse width is employed in resonant clock drivers to further decrease energy consumption, since the clock driver only needs to be active long enough to restore the energy that is lost in the portions (sectors) of the resonant clock distribution network that is being driven by the individual clock drivers.
Mode changing in a resonant clock distribution network is needed for variable operating frequency, for example, in a processor integrated circuit with “turbo” operating modes or in which voltage-frequency scaling is employed to reduce energy consumption when processor activity is low. The mode changing may change operating frequency and/or may change the clock mode from resonant distribution to non-resonant, while adjusting the drive pulse width. However, when changing the pulse width in a resonant clock distribution network, the latency of the clock signals changes. Such changes generate timing errors that may cause improper operation of the integrated circuit in which the resonant clock distribution network is implemented.
It would therefore be desirable to provide a control scheme for a resonant clocking circuit that can change drive pulse width during operation without causing clock glitches.